Non-volatile memory (NVM) is the general term used to describe the type of memory that retains its data even when power is turned off, and this sort of memory is typically used to store data that must not be lost when a device incorporating the memory looses power. Such devices include computers, CD-ROMs, mobile phones, digital cameras, compact flash cards, mp3 players and Micro-Controller Units (MCUs) from the automotive, aero and other industries.
Types of non-volatile memory include Read Only Memory (ROM), Electrically Programmable Read Only Memory (EPROM), Electrically Erasable and Programmable Read Only Memory (EEPROM), Flash EEPROMs, Non-Volatile Static Random Access Memory (NVSRAM), Ferroelectric Random Access Memory (FeRAM), and the like.
Whilst some non-volatile memory is purely “read only”, with the “programming” being done by hard-coding the data during the memory fabrication process, other types are programmed electrically post-fabrication.
One type of programmable non-volatile memory the present invention relates to is Electrically Erasable and Programmable Read Only Memory (EEPROM), however the invention may equally be applied to other non-volatile memory types listed above. Electrically Erasable and Programmable Read Only Memory (EEPROM) can be split into two sub types: byte erasable and Flash EEPROM. As the name suggests, the byte erasable type can be erased and written in byte size chunks, whilst flash memory is written in byte (or larger) sized chunks, but is erased in sections (which are multiple bytes in size). The size of the sections erased in flash memory is part specific, and can be anywhere in size from meaning the entire memory array of the device to only a sub-portion, or sector, comprising a small number of individual bytes.
EEPROMs store information by storing charge on an insulated piece of semiconductor material, known as the floating gate. Typically, the insulating material is a layer of Silicon Dioxide. As is known in the art, this charge is moved onto the insulated material forming the memory cell by either Hot Carrier Injection (HCI) or Fowler-Nordheim Tunnelling (FNT). Each individual memory cell can store a single bit of information, thus they are often referred to as bitcells.
Briefly, Hot Carrier Injection (via either Hot holes, i.e. positive charges, or Hot electrons, i.e. negative charges) works by applying a large voltage bias across the channel of the bitcell, resulting in the “heating”, i.e. energy injection, of the carriers within the channel, which provides some of them with enough energy to surmount the silicon dioxide energy barrier, and thus are “injected” into the insulated material.
Meanwhile, Fowler-Nordheim tunnelling works by applying a high electric field between the gate of the bitcell and either the source or drain. Assuming the field is high enough, this high electric field lowers the height of the energy barrier of the silicon dioxide layer and thus allows electrons to “tunnel” across the insulated material and onto the floating gate forming the bitcell.
When there is little or no charge on the floating gate, the threshold voltage Vt of the transistor forming the bitcell is low. As charge is moved onto the floating gate during programming by the above methods, the threshold voltage Vt of the bitcell increases. Once the amount of charge stored on the floating gate reaches a predetermined level, the bitcell is considered programmed.
The predetermined level of charge that signifies a programmed state is arbitrary, but must be high enough to be easily distinguished from the unprogrammed state.
The movement of this charge onto or off the floating gate is known as “programming” (of the bitcell). However, “programming” does not in itself refer to a particular data state of the bitcell (1 or 0), because due to possible logical inversion at the output from the core memory array and/or the output to the data bus, the programmed state may correspond to either a logic 1 or 0. For this reason, in the following description it will be assumed that “programmed” means that charge has been stored on the floating gate, resulting in a high threshold voltage Vt, whilst “unprogrammed” means that little or no charge is stored in the floating gate, thus a low Vt.
Memory bitcells are read by applying the correct bias voltages to the bitcell and measuring the resultant current flow using current senseamps. The read voltages are set such that if the threshold voltage Vt is high, due to the bitcell being programmed, then little or no current flows, so little or nothing is detected by the senseamp. Conversely, if the threshold voltage Vt is low, due the to the bitcell being unprogrammed, significantly more current flows that is detected by the senseamp. Multiple cells may be read at one time, by using multiple senseamps.
Since, in a typical memory array, there are multiple bitcells connected to the same bitlines, wordlines and sourcelines, problems can occur if the applied voltages and currents are not perfectly matched to the requirements of the bitcell being programmed. In other words, applying incorrect voltages and currents to the array can result in unintentional erasure or programming of the other bitcells not currently being programmed. These arise during programming and erasing, and are commonly referred to as disturbs.
In the case of flash memory, the array gets erased on an erase sector granularity (an erase sector being a predefined number of bitcells). However, bitcells may be programmed on a bit by bit basis. Therefore, there are two types of unintended disturbs that may occur on erased bitcells, during the intended programming of another bitcell in the same high voltage sector:
1. Row disturb—occurs on bitcells sharing the same wordline but on a different bitline to the intended target bitcell. The Vgs (i.e. the voltage across the gate and source of the transistor forming the bitcell) of those bitcells is characterised as (Vpwl—(unselected bitline voltage)), where Vpwl is the voltage applied to the selected wordline during programming. In order to avoid row disturb, the Vgs should be negative enough to avoid generation of hot electrons in the channel of the unselected bitcell. This is called maintaining a row disturb margin.
2. Bitline disturb—occurs on bitcells sharing the same bitline but on a different wordline to the intended target bitcell (but in the same high voltage sector). This disturb mechanism is only applicable if the high voltage sector is bigger than a single wordline. The Vgs of those cells is (0V—(selected bitline voltage)). Similarly, in order to avoid bitline disturb, this Vgs must be negative enough to avoid the generation of hot electrons in the channel. It also has to be ensured that selected bitlines will never reach potentials too low to create such a disturb, but they need to be driven low enough to allow proper programming of the bitcells intended to be programmed.
As is known in the art, the above described physical methods used to program the bitcells are carried out by biasing the terminals of the bitcell to be programmed (or read, or erased) with the correct voltages. These bias voltages are derived from reference voltages.
Prior art systems for producing the necessary reference voltages make use of certain physical device parameters to derive the required voltages. This is to say, they create the required voltages by using multiple semiconductor devices with certain physical dimensions that result in predetermined voltage drops across each of them, for example transistors, zener diodes and the like. These devices are then stacked up to produce the required voltage drop.
The problem with such prior art systems is that they rely on the relative physical dimensions as well as diffusion levels of the devices used to determine the levels of the bias voltages, which are subject to manufacturing tolerances. Thus, when a design of such prior art arrangements is transferred to silicon and the resulting device tested, in view of the manufacturing tolerances changes in the design may be required in order to achieve the required bias voltage levels. This requires changes in masks and may require several mask change iterations and is thus time consuming and costly. Moreover, since these parameters are fixed during manufacture, they cannot be subsequently changed, for example, to compensate for operating temperate range changes. The only way to change these parameters is to redesign the physical parameters of the devices used, and then manufacture a whole new device with the new parameters. This is a costly and time consuming process. Further, since manufacturing tolerances are involved in setting the device characteristics, redesigns might not even solve any issue with the final product. In this case, a solution may be to selectively pick the devices that exhibit the required characteristics, with the remainder being wasted (and/or used in applications with lower specification requirements). This obviously affects production yield of such non-volatile memory devices considerably.
In addition, in order to provide bias voltages having the required levels to achieve the required disturb margins, the prior art zener stack arrangements require certain zener elements (such as transistor FETodes) which evices can have undesirable electrical behaviour.
Accordingly, it would be desirable to provide an improved voltage generator for a non-volatile memory array which overcomes or at least alleviates some or all of the above referenced problems.